The present invention pertains to a semiconductor memory, and in particular to a SRAM (static random access memory).
As shown in FIG. 30, a general memory cell in an existing SRAM is constituted with six MOS (metal oxide semiconductor) transistors 300-310. In this memory cell, PMOS (p-channel MOS) transistor 300 and NMOS (n-channel MOS) 302, and PMOS transistor 304 and NMOS transistor 306 constitute CMOS (complementary MOS) inverters 312 and 314, respectively. These CMOS inverters 312 and 314 are cross-coupled and cross-connected to constitute a latch circuit or flip-flop. Both of the NMOS transistors 308 and 310 constitute a transfer gate for electrically closing or opening (breaking) the circuit between data storage nodes (N1) and (N2), that are Finished with a pair of complementary cross-coupled nodes in this flip-flop, and bit line pair (BL) and (BLxe2x88x92).
When data are written to this memory cell, both transfer gates 308 and 310 turn on due to word line (WL) being activated to the high level. A pair of voltage signals that have complementary logic levels that are already supplied onto bit line pair (BL) and (BLxe2x88x92) are input (written) to their respective data storage nodes (N1) and (N2).
During standby mode when data are held, both transfer gates 308 and 310 will be off, and the logic level of data storage nodes (N1) and (N2) is held by the data latch function of the flip-flop.
When data are read from this memory cell, after bit line pair (BL) and (BLxe2x88x92) are brought to a high-impedance state, both of the transfer gates 308 and 310 will be on by word line (WL) being activated to the high level. A pair of voltage signals that have complementary logic levels is output onto bit line pair (BL) and (BLxe2x88x92) from data storage nodes (N1) and (N2), the potential difference between this bit line pair (BL) and (BLxe2x88x92) is detected and amnplified by a sense amplifier (not shown) and 1 bit of data is read.
With six-transistor SRAM cells such as the one described above, the data hold part is constituted with a flip-flop and leakage current that flows to one transistor that is off in each CMOS inverter 312 and 314 is quickly absorbed or replenished by the other transistor that is on. Thus, the potential of data storage nodes (N1) and (N2) is held stably in a static state and high-speed write/read operations are possible without requiring a refresh operation. However, there is the disadvantage that the circuit requires six transistors, making the memory cell array large. Compared to a DRAM (dynamic RAM) that is constituted with one transistor and one capacitor, general-purpose six-transistor SRAM cells require an appreciably larger layout area about 8 times with the same process).
The present invention was conceived in light of these problems of the prior art. Its objective is to provide a static type semiconductor memory cell and semiconductor memory device with which a reduced layout area will be realized while ensuring that data are held reliably.
Another objective of the present invention is to provide a static type semiconductor memory cell and semiconductor memory with which a reduced layout area will be realized while ensuring that that data are written and read reliably and at high speed.
In order to realize the aforementioned objectives, the semiconductor memory cell of the present invention is constituted with a data storage node that electrically stores 1 bit of data in the form of a voltage logic level; a first transistor connected between the bit line and the aforementioned data storage node and the control terminal of which is connected to the word line; a second transistor connected between the aforementioned data storage node and a first reference voltage terminal that provides a first reference potential that has a prescribed logic level; and an inverter circuit, the input terminal of which is connected to the aforementioned data storage node and the output terminal of which is connected to the control terminal of the aforementioned second transistor, which outputs a voltage to the aforementioned output terminal at a logic level opposite that of the voltage input to the aforementioned input terminal.
Also, the semiconductor memory device of the present invention is constituted with the aforementioned semiconductor memory cell; a data write means for writing the desired data to the data storage node of the aforementioned semiconductor memory cell, which drives the aforementioned bit line to a potential at a logic level that corresponds to the value of the aforementioned data and also drives the aforementioned word line to a prescribed potential to turn on the aforementioned first transistor; and a data read means for reading data stored in the data storage node of the aforementioned semiconductor memory cell, which drives the aforementioned word line to a prescribed potential to turn the aforementioned first transistor on after the aforementioned bit line is precharged to a potential at a logic level opposite that of the aforementioned first reference potential, and that thereby outputs the aforementioned stored data on the basis of the temporal change of the potential of the aforementioned bit line.
With the semiconductor memory cell of the present invention, the first transistor functions as a transfer gate and there is electrical conduction or non conduction between the bit line and the data storage node according to the word line potential. The second transistor constitutes a latch circuit that works in conjunction with the inverter circuit and it will be on or off directly according to the logical value of the output of the inverter circuit and indirectly according to the logic value of the potential that is written to or held by the data storage node.
In the semiconductor memory device of the present invention, in order to perform the data write operation at high speed, the aforementioned data write means should preferably be constituted to include a reference voltage control means that makes the potential of the aforementioned first reference voltage terminal higher or lower by a prescribed amount relative to the standard reference potential in order to reduce the current flow through the aforementioned second transistor when the aforementioned date write means writes data at a logic level opposite that of the aforementioned first reference potential to the aforementioned data storage node. Or, the aforementioned data write means should also be constituted to include an inversion acceleration means that speeds up the inversion of the logic level of the output of the aforementioned inverter circuit in order to decrease the switching time of the aforementioned second transistor from on to off when the aforementioned data write means writes data at a logic value opposite that of the aforementioned first reference potential to the aforementioned data storage node.
Also, in order to perform data read operation at high speed, in the semiconductor memory device of the present invention, the aforementioned data read means should preferably be constituted to include a reference voltage control means that raises or lowers the potential of the aforementioned first reference voltage terminal by a prescribed amount in order to reduce current that flow through the aforementioned second transistor when data stored in the data storage node of the aforementioned semiconductor memory cell are read.
In the semiconductor memory cell of the present invention, when the second transistor turns on, the logic value of the potential of the data storage node is the same as the logic value of the aforementioned first reference voltage terminal and is held in a static state.
Also, when the second transistor turns off, the potential of the data storage node has a logical value that is the opposite that of the aforementioned first reference potential and it is held in a floating state. In this case, leakage current in the second transistor, which is off, will operate to change the potential of the data storage node toward the potential of the first reference voltage terminal, that is, the logic level opposite that of the logic level currently held. However, in the first transistor, leakage current flows that will absorb or cancel the leakage current of the second transistor, so that the logic level (stored data) of the data storage node potential can be held reliably.
The semiconductor memory device of the present invention, in order to increase the reliability at which data are held during the standby period, should preferably be constituted with a data hold current control means that supplies current for holding data stored in the aforementioned data storage node via the aforementioned first transistor and control the aforementioned data hold current at the potential of the aforementioned word line.
In one form of the present invention, the data hold current control means comprises a monitoring node; a third transistor connected between a second supply voltage terminal that provides a prescribed reference potential at a logic level opposite that of the aforementioned reference potential and the aforementioned monitoring node; a fourth transistor connected between the aforementioned monitoring node and a third supply voltage terminal that provides a prescribed reference potential at the same logic level as the aforementioned first reference potential; an inverter circuit, the input terminal of which is connected to the aforementioned monitoring node, the output terminal of which is connected to the aforementioned fourth transistor control terminal, and that outputs voltage to the aforementioned output terminal at a logic level opposite that of the voltage input to the aforementioned input terminal; an initialization means that initializes the aforementioned monitoring node to a potential that has a logic level for keeping the aforementioned fourth transistor turned on; a monitor control means that controls the potential of the control terminal of the aforementioned third transistor so that the current that flows through the aforementioned third transistor will gradually increase with time after the aforementioned initialization; a word line potential control means that controls the potential of the aforementioned word line so that the current that flow through the aforementioned first transistor will gradually increase with time after the aforementioned initialization; and a reset means that stops the control operation of the aforementioned word line potential control means and returns the potential of the aforementioned word line to a prescribed reference level when the potential of the aforementioned monitoring node reaches a logic level opposite that of the logic level at the time of the aforementioned initialization. In this constitution, a resistor should preferably be connected in series with the aforementioned fourth transistor between the aforementioned monitoring node and the aforementioned third supply voltage terminal. The aforementioned third and fourth transistors could also have the essentially same transistor structure as the aforementioned first and second transistors, respectively, and they could be produced with the same process on the same semiconductor chip.
And in another form of the present invention, the aforementioned data hold current control means has a word line potential switching means that repeatedly switches at a fixed cycle between a first time when the aforementioned word line is brought to an active first potential and a second time when it is brought to an inactive second potential.
In this case, the aforementioned data hold current control means should also preferably comprise a monitoring node; a third transistor connected between the aforementioned monitoring node and a second supply voltage terminal that provides a second reference potential at a logic level opposite that of the aforementioned first reference potential; a fourth transistor connected between the aforementioned monitoring node and a third supply voltage terminal that provides a third reference potential at the same logic level as the aforementioned first reference potential; an inverter circuit, the input terminal of which is connected to the aforementioned monitoring node, and the output terminal of which is connected to the control terminal of the aforementioned fourth transistor, and that outputs voltage to the aforementioned output terminal at a logic level opposite that of the voltage input to the aforementioned input terminal; an initialization means that precharges the aforementioned monitoring node to a potential at a logic level for keeping the aforementioned fourth transistor turned on; and a monitor control means that drives the control terminal of the aforementioned third transistor to a prescribed potential after the start of the aforementioned first time to source current between the third supply voltage terminal and the aforementioned monitoring node via the aforementioned third transistor, and that provides a signal for switching from the aforementioned first time to the aforementioned second time to the aforementioned word line potential switching means when the potential of the aforementioned monitoring node reaches a logic level opposite that of the logic level at the time of the aforementioned initialization.
The semiconductor memory device of the present invention should also preferably have a refresh control means that, during a write cycle where the desired data are written to the aforementioned semiconductor memory cell selected in the memory cell array, drives all of the bit lines of the aforementioned memory cell array to a potential with a prescribed logic level for a prescribed time independently of the time during which the aforementioned word line is enabled for writing data to the aforementioned selected semiconductor memory cell, and also drives all of the aforementioned word lines to a prescribed potential makes the aforementioned first transistors in all of the aforementioned semiconductor memory cells conduct. Or it could also have a refresh control means that, during a read cycle during which stored data are read from the aforementioned semiconductor memory cell selected in a memory cell array, drives all the bit lines in the aforementioned memory cell array to a potential at a prescribed logic level for a prescribed time independently of the time during which the aforementioned word line is enabled to read data for the aforementioned semiconductor memory cell, and that also drives all of the word lines to a prescribed potential to make the aforementioned first transistors in all of the aforementioned semiconductor memory cells conduct.